3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU-Reference-Cited by-同舟云学术

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3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU

Published:2022-02-20 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Wuu John¹,Agarwal Rahul²,Ciraula Michael¹,Dietz Carl¹,Johnson Brett¹,Johnson Dave¹,Schreiber Russell³,Swaminathan Raja³,Walker Will¹,Naffziger Samuel¹

Affiliation:

1. AMD,Fort Collins,CO

2. AMD,Santa Clara,CA

3. AMD,Austin,TX

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731565.pdf?arnumber=9731565

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3. Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip Architectures;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08

4. Review of chiplet-based design: system architecture and interconnection;Science China Information Sciences;2024-07-19

5. Native DRAM Cache: Re-architecting DRAM as a Large-Scale Cache for Data Centers;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

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