Author:
Gauhar Sameen,Sharif Adeeba,Alam Naushad
Cited by
5 articles.
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1. Experimental analysis of the symmetry of approximate adder designs in FPGA and ASIC;2023 XIII Brazilian Symposium on Computing Systems Engineering (SBESC);2023-11-21
2. Performance Evaluation of Adder Architectures for Vedic Multiplier Implementation;2023 4th IEEE Global Conference for Advancement in Technology (GCAT);2023-10-06
3. Comparative Study of Parallel Prefix Adders Based on Carry Propagation and Sum Propagation;2023 International Conference on Power, Instrumentation, Control and Computing (PICC);2023-04-19
4. Area and Delay Efficient Hybrid Prefix Adders for Residue Number System Applications;2023 IEEE 12th International Conference on Communication Systems and Network Technologies (CSNT);2023-04-08
5. An Area and Delay-Efficient Approximate Hybrid Adder for VLSI Circuit Designs;Lecture Notes in Electrical Engineering;2022