32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique-Reference-Cited by-同舟云学术

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32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique

Published:2021-02-13 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Kim Juyeop,Jo Yongwoo,Lim Younghyun,Seong Taeho,Park Hangi,Yoo Seyeon,Lee Yongsun,Choi Seojin,Choi Jaehyouk

Funder

Samsung

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9365732/9365735/09365815.pdf?arnumber=9365815

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 10.5 A 76 fs_rms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

2. 14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

3. 10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fs_rms Integrated Jitter and −252.4dB FoM;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

4. A 12.8–15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation;IEEE Journal of Solid-State Circuits;2024-02

5. Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop;IEEE Journal of Solid-State Circuits;2024

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