27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering
Author:
Funder
Beijing Innovation Center for Future Chip
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9365732/9365735/09366008.pdf?arnumber=9366008
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2. A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC;IEEE Journal of Solid-State Circuits;2024-08
3. A 200kHz-bandwidth 101dB SNDR noise-shaping SAR ADC with NTF strengthening method;IEICE Electronics Express;2024-07-10
4. An Improved Foreground Calibration Method for Capacitor Mismatch in NS-SAR ADC;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
5. Loop Filter Design Considerations for Noise-Shaping in SAR ADCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
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