24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology

Author:

Fritsch Alexander,Joshi Rajiv,Chakraborty Sudipto,Wetter Holger,Srinivasan Uma,Hyde Matthew,Torreiter Otto,Kugel Michael,Radko Dan,Kim Hyong,Friedman Daniel

Publisher

IEEE

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Fast and Robust Sense Amplifier for Digital In Memory Computing;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01

2. Single-Bit Architecture for Low Power IoT Applications;Lecture Notes in Networks and Systems;2022-12-13

3. Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing;IEEE Journal of Solid-State Circuits;2022

4. Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-08

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