Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing-Reference-Cited by-同舟云学术

Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing

Published:2022-02-20 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Gomes Wilfred¹,Koker Altug²,Stover Pat³,Ingerly Doug¹,Siers Scott²,Venkataraman Srikrishnan⁴,Pelto Chris¹,Shah Tejas⁵,Rao Amreesh²,O'Mahony Frank¹,Karl Eric¹,Cheney Lance²,Rajwani Iqbal²,Jain Hemant⁴,Cortez Ryan²,Chandrasekhar Arun⁴,Kanthi Basavaraj⁴,Koduri Raja⁶

Affiliation:

1. Intel,Portland,OR

2. Intel,Folsom,CA

3. Intel,Chandler,AZ

4. Intel,Bengaluru,India

5. Intel,Austin,TX

6. Intel,Santa Clara,CA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731673.pdf?arnumber=9731673

Reference6 articles.

1. A 10nm High Performance and Low-Power CMOS Technology;auth;IEDM,2017

2. Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs;burton;IEEE Applied Power Electronics Conf,0

3. Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12x12mm2, 1 mm Package-on-Package;gomes;ISSCC,2020

4. Integrated Voltage Regulator Efficiency Improvement using Coaxial Magnetic Composite Core Inductors

5. Embedded Multidie Interconnect Bridge—A Localized, High-Density Multichip Packaging Interconnect

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