A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS
Author:
Affiliation:
1. Eindhoven University of Technology,Eindhoven,The Netherlands
2. NXP Semiconductors,Eindhoven,The Netherlands
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731789.pdf?arnumber=9731789
Reference6 articles.
1. A Simultaneous Multiband Continuous-Time ΔΣ ADC With 90-MHz Aggregate Bandwidth in 40-nm CMOS
2. 16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter
3. A 13.3 mW 60 MHz Bandwidth, 76 dB DR 6 GS/s CT??M with Time Interleaved FIR Feedback;jain;IEEE Symp VLSI Circuits,2016
4. Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta–Sigma Modulator
5. A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving −164-dBFS/Hz NSD
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1. Using Negative-R Assisted Integrators in Wide-band Delta-Sigma Modulators;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. Comparative Study for Different Loop-Filter Architectures of 2x Time-Interleaved CT DSM;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12
4. Design Techniques for Energy-Efficient Analog-to-Digital Converters;IEEE Open Journal of the Solid-State Circuits Society;2023
5. Wideband Continuous-Time MASH Delta-Sigma Modulators: A Tutorial Review;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-06
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