A 65nm CMOS, 3.5-to-11GHz, Less-Than-1.45LSB-INL<sub>pp</sub>, 7b Twin Phase Interpolator with a Wideband, Low-Noise Delta Quadrature Delay-Locked Loop for High-Speed Data Links-Reference-Cited by-同舟云学术

A 65nm CMOS, 3.5-to-11GHz, Less-Than-1.45LSB-INL_pp, 7b Twin Phase Interpolator with a Wideband, Low-Noise Delta Quadrature Delay-Locked Loop for High-Speed Data Links

Published:2022-02-20 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Wang Zhaowen¹,Kinget Peter R.¹

Affiliation:

1. Columbia University,New York,NY

Funder

Analog Devices

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731649.pdf?arnumber=9731649

Reference8 articles.

1. 1A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7GHz Clock Generator in 65nm with 7b Phase Interpolators for High-Speed Data Links;wang;ISSCC,2021

2. A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET

3. A 4-to-11 GHz injection-locked quarter-rate clocking for an adaptive 153fJ/b optical receiver in 28nm FDSOI CMOS;raj;ISSCC,2015

4. 30.7 An 8b Injection-Locked Phase Rotator with Dynamic Multiphase Injection for 28/56/112Gb/s Serdes Application

5. 8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS

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