A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET-Reference-Cited by-同舟云学术

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A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET

Published:2018-02 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Solid - State Circuits Conference - (ISSCC)
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Author:

Chen Stanley,Zhou Lei,Zhuang Ian,Im Jay,Melek Didem,Namkoong Jinyung,Raj Mayank,Shin Jaewook,Frans Yohan,Chang Ken

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8304413/8310156/08310348.pdf?arnumber=8310348

Cited by 30 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. A Digital Pre-Distortion Technique for High-Linearity, Low-Power, Compact, Phase Interpolators;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. A 4-to-16GHz Dual-Loop PLL Based on Current-Control RO and Calibration in a 6-nm FinFET;2024 13th International Conference on Communications, Circuits and Systems (ICCCAS);2024-05-10

4. 7.9 An 8b 6-12GHz 0.18mW/GHz DC Modulated Ramp-Based Phase Interpolator in 65nm CMOS Process;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

5. A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement;IEEE Journal of Solid-State Circuits;2023-10

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