Signal Integrity Analysis of Wire Bonding Finger Capacitance to Reduce the Reflection of Multi-drop Topology for Low-Power Double Data Rate (LPDDR)
Author:
Affiliation:
1. Korea Advanced Institute of Science and Technology,Daejeon,Korea, Republic of South
2. SK hynix,Icheon,Korea, Republic of South
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10241361/10241364/10241728.pdf?arnumber=10241728
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3. Non-Target DRAM Termination in High Speed LPDDR System for Improved Signal Integrity
4. High-k and ultra-low-loss BADCy/Ni0.5Ti0.5NbO4 composites for PCB application fabricated by cold isostatic pressing and vacuum assisted infiltration processes
5. Study of Thickening Soldermask Coated Microstrip Lines on High-Speed PCBs for Crosstalk Reduction in DDR5
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Signal Integrity Analysis and Design for Cascaded Wire Bonding of Low-Power Double Data Rate (LPDDR);2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa);2024-05-20
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