Design of FinFET and GnrFET Based Full Adder Cell Using Multiplexer Selection Logic-Reference-Cited by-同舟云学术

Design of FinFET and GnrFET Based Full Adder Cell Using Multiplexer Selection Logic

Published:2022-01-20 Issue: Volume: Page:
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Container-title:2022 4th International Conference on Smart Systems and Inventive Technology (ICSSIT)
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Author:

Florance D. Rebecca¹,Prabhakar B.²

Affiliation:

1. JNTU College of Engineering,Dept. of ECE,Hyderabad,Telangana,India

2. JNTU College of Engineering,Dept. of ECE,Jagtial,Telangana,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9716239/9716227/09716389.pdf?arnumber=9716389

Reference22 articles.

1. Hybrid logical effort for hybrid logic style full adders in multistage structures;tooraj;IEEE Trans Very Large Scale Integration (VLSI) Systems,2019

2. A transistor-level probabilistic approach for reliability analysis of arithmetic circuits with applications to emerging technologies;bodapati;IEEE Transactions on Reliability,2017

3. Modelling for triple gate spin-FET and design of triple gate spin-FET-based binary adder;gul faroz ahmad;IET Circuits Devices & Systems,2020

4. Proposal for multi-gate spin field-effect transistor;gefei;IEEE Transactions on Magnetics,2018

5. A carry lookahead adder based on hybrid CMOS-memristor logic circuit;gongzhi;IEEE Access,2019

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1. Review of the Nanoscale FinFET Device for the Applications in Nano-regime;Current Nanoscience;2023-09

2. Design and analysis of a low power high speed full adder using 2×1 multiplexer;2022 IEEE North Karnataka Subsection Flagship International Conference (NKCon);2022-11-20