Design techniques for reference clock jitter optimization for high speed PHYs-Reference-Cited by-同舟云学术

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Design techniques for reference clock jitter optimization for high speed PHYs

Published:2023-11-01 Issue: Volume: Page:
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Container-title:2023 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS)
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Author:

Krishnan Rohini¹,Potphode Tejas P¹,Sharma Ashish²,Zhang Haijin³,Hu Herry³,Mulvihill David R⁴

Affiliation:

1. Intel Technology India Pvt. Ltd,Networking Group,Bangalore,India

2. Intel Technology India Pvt. Ltd,Power Solutions Group,Bangalore,India

3. Intel Corporation,Power Solutions Group,Shanghai,China

4. Intel Corporation,IP Design Group,Fort Collins,Colorado,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10347563/10348175/10348250.pdf?arnumber=10348250

Reference11 articles.

1. Investigating the Impact of Supply Noise on the Jitter in Gigabit I/O Interfaces

2. Optimizing the output impedance of a power delivery network for microprocessor systems

3. Modeling and Correlation of Supply Noise for a 3.2GHz Bidirectional Differential Memory Bus;Schmitt;DesignCon,2005

4. Comparison of on-die global clock distribution methods for parallel serial links

5. Prediction and Measurement of Supply Noise Induced Jitter in High-Speed I/O Interfaces;Lan;DesignCon,2009

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