Author:
Papachristou C.A.,Pandya A.L.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
4 articles.
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1. Determination of the delay of a programmable logic array;Russian Microelectronics;2010-07
2. False path exclusion in delay analysis of RTL structures;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2002-02
3. River PLAs: a regular circuit structure;Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324);2002
4. Whirlpool PLAs: a regular logic structure and their synthesis;IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.