Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation-Reference-Cited by-同舟云学术

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Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation

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Container-title:International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)
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Author:

Wong H.-S.P.,Frank D.J.,Solomon P.M.

Publisher

IEEE

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