High performance dual-gate sub-halfmicron CMOSFETs with 6 nm-thick nitride SiO/sub 2/ films in an N/sub 2/O ambient-Reference-Cited by-同舟云学术

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High performance dual-gate sub-halfmicron CMOSFETs with 6 nm-thick nitride SiO/sub 2/ films in an N/sub 2/O ambient

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Container-title:International Technical Digest on Electron Devices
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Author:

Uchiyama A.,Fukuda H.,Hayashi T.,Iwabuchi T.,Ohno S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/878/6081/00237141.pdf?arnumber=237141

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2. Stacked Gate-All-Around Nanosheet Channel Ferroelectric Hf_xZr_1-xO₂ FETs With NH₃ Plasma Treatment Featuring High Footprint Current;2023 Silicon Nanoelectronics Workshop (SNW);2023-06-11

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4. Hysteresis-Free Gate-All-Around Stacked Poly-Si Nanosheet Channel Ferroelectric Hf_xZr_1-xO₂ Negative Capacitance FETs With Internal Metal Gate and NH₃ Plasma Nitridation;IEEE Transactions on Electron Devices;2022-03

5. Negative bias temperature instability of SiC MOSFET induced by interface trap assisted hole trapping;Applied Physics Letters;2016-01-04

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