Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses-Reference-Cited by-同舟云学术

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Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses

Published:2021-04 Issue:4 Volume:68 Page:1461-1470
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Hsueh Cheng-Yun,Ker Ming-Dou

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9385809/09372137.pdf?arnumber=9372137

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Efficient Silicon-Controlled Rectifier Devices for Cross-Power-Domain ESD Protections;IEEE Transactions on Electron Devices;2024-08

2. Test Structures of Cross-Domain Interface Circuits with Deep N-Well Layout to Improve CDM ESD Robustness;2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS);2024-04-15

3. Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors;IEEE Journal of the Electron Devices Society;2023

4. Validation Technique for Thin Oxide CDM Protections;2022 International Semiconductor Conference (CAS);2022-10-12

5. A Study on ESD-CDM Cross-Power Domain Failures;2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2022-06-12

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