Modeling of gate oxide shorts in MOS transistors-Reference-Cited by-同舟云学术

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Modeling of gate oxide shorts in MOS transistors

Published:1989-03 Issue:3 Volume:8 Page:193-202
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Syrzycki M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx1/43/883/00021839.pdf?arnumber=21839

Cited by 35 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Structured Test Development Approach for Computation-in-Memory Architectures;2022 IEEE International Test Conference in Asia (ITC-Asia);2022-08

2. Gate-oxide-short defect analysis and fault modeling in FinFETs;Microelectronics Reliability;2022-02

3. Gate Oxide Short Defect Model in FinFETs;Journal of Electronic Testing;2018-04-14

4. Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2014-06

5. On modeling faults in FinFET logic circuits;2012 IEEE International Test Conference;2012-11

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