Author:
Vinod Nirmal,Neelakandan KV Abhishek,Udith R,Sayooj Devadas K,Dinesh Kovvuri,Chalil Anu,Sreehari KN
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design and Performance Analysis of Configurable Logic Block (CLB) for FPGA using Various Circuit Topologies;2024 3rd International Conference for Innovation in Technology (INOCON);2024-03-01
2. In-Memory Fault-Free Vector Simulation;2023 IEEE East-West Design & Test Symposium (EWDTS);2023-09-22
3. In-Memory Fault as Address Simulation;2023 IEEE East-West Design & Test Symposium (EWDTS);2023-09-22
4. VECTOR-LOGICAL FAULT SIMULATION;Radio Electronics, Computer Science, Control;2023-06-29
5. Vector–Logic Synthesis of Deductive Matrices for Fault Simulation;Èlektronnoe modelirovanie;2023-04-24