Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs-Reference-Cited by-同舟云学术

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Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Published: Issue: Volume: Page:
ISSN:
Container-title:IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.
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Author:

Goto K.,Satoh S.,Ohta H.,Fukuta S.,Yamamoto T.,Mori T.,Tagawa Y.,Sakuma T.,Saiki T.,Shimamune Y.,Katakami A.,Hatada A.,Morioka H.,Hayami Y.,Inagaki S.,Kawamura K.,Kim Y.,Kokura H.,Tamura N.,Horiguchi N.,Kojima M.,Sugii T.,Hashimoto K.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/9719/30682/01419111.pdf?arnumber=1419111

Cited by 31 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The Analysis of the Process-Induced Channel Stress in N-MOSFET;Advanced Materials Research;2013-05

2. The effect of Young's modulus of contact-etch-stop layer (CESL) stressor on the strained-Si MOSFET;physica status solidi (a);2012-09-24

3. Enhancement of SiN-induced compressive and tensile strains in Si free-standing microstructures by modulation of SiN network structures;Thin Solid Films;2012-02

4. Performance Prediction of Complementary Field-Effect Transistor Circuits Using Graphene with Band Gap Induced by Site-Potential Asymmetry;Japanese Journal of Applied Physics;2011-10-27

5. Advanced strain engineering for state-of-the-art nanoscale CMOS technology;Science China Information Sciences;2011-05

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