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Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips

  • Published:2020-06 Issue:6 Volume:39 Page:1191-1204
  • ISSN:0278-0070
  • Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • language:
  • Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Chen SongORCID,Ge Mengke,Li Zhigang,Huang JingleiORCID,Xu QiORCID,Wu Feng

Funder

National Natural Science Foundation of China

Beijing Municipal Science and Technology Program

Fundamental Research Funds for the Central Universities

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Systematic Construction of Deadlock-Free Routing for NoC Using Integer Linear Programming;2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2023-12-18

2. Multiobjective piecewise regressive elitism spotted hyena optimized mapping for 3D NoC architecture design;International Journal of Information Technology;2023-05-25

3. Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization;International Journal of Swarm Intelligence Research;2023-04-20

4. Mapping of Cores onto Network on Chip Architectures by Hierarchical Genetic Evolution Algorithm;Lecture Notes in Electrical Engineering;2023

5. Fault-Tolerant Core Mapping for NoC based architectures with improved Performance and Energy Efficiency;2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2022-10-24
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