Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes-Reference-Cited by-同舟云学术

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Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes

Published:2017-08 Issue:8 Volume:36 Page:1265-1273
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Panth Shreepad^ORCID,Samal Sandeep Kumar^ORCID,Samadi Kambiz,Du Yang,Lim Sung Kyu

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/7982827/07875489.pdf?arnumber=7875489

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. INVITED: Design Automation Needs for Monolithic 3D ICs: Accomplishments and Gaps;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

2. Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective;Integration;2022-07

3. High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-06

4. Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations;ACM Journal on Emerging Technologies in Computing Systems;2021-04

5. A Test Response Compression Method for Monolithic 3-D ICs Based on 3-D Haar Wavelet Transforms;IEEE Transactions on Instrumentation and Measurement;2021

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