Author:
Chiao-Ling Lung ,Yu-Shih Su ,Hsih-Hsiu Huang ,Yiyu Shi ,Shih-Chieh Chang
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
12 articles.
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2. Circuit and Methodology for Testing Small Delay Faults in the Clock Network;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018-10
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5. References;Three-Dimensional Integrated Circuit Design;2017