Circuit and Methodology for Testing Small Delay Faults in the Clock Network

Author:

Yang Shao-Fu,Wen Zhi-Yuan,Huang Shi-Yu,Tsai Kun-Han,Cheng Wu-Tung

Funder

Ministry of Science and Technology, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Duty-Cycle Monitor Supporting A Wide Frequency Range of Clock Signal;2021 IEEE International Test Conference in Asia (ITC-Asia);2021-08-18

2. Overview of On-Chip Performance Monitors for Clock Signals;2020 IEEE 29th Asian Test Symposium (ATS);2020-11-23

3. Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter;2020 IEEE International Test Conference (ITC);2020-11-01

4. Online Testing of Clock Delay Faults in a Clock Network;2019 IEEE International Test Conference in Asia (ITC-Asia);2019-09

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