Author:
Dusung Kim ,Ciesielski M.,Seiyang Yang
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
4 articles.
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1. RepCut: Superlinear Parallel RTL Simulation with Replication-Aided Partitioning;Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3;2023-03-25
2. Gate-level Circuit Partitioning Algorithm Based on Cut Vertex and Betweenness Centrality;2022 34th Chinese Control and Decision Conference (CCDC);2022-08-15
3. A compact real-time simulator with spatial-temporal parallel design for large-scale wind farms;CSEE Journal of Power and Energy Systems;2022
4. Verilog HDL Simulator Technology: A Survey;Journal of Electronic Testing;2014-05-23