1. Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning
2. Scalable parallel event-driven HDL simulation for multi-cores
3. Krste Asanović , Rimas Avižienis , Jonathan Bachrach , Scott Beamer , David Biancolin , Christopher Celio , Henry Cook , Daniel Dabbelt , John Hauser , and Adam Izraelevitz . 2016. The Rocket Chip Generator. EECS Department , University of California , Berkeley, Tech . Rep. UCB/EECS- 2016 -17, 4 (2016). Krste Asanović, Rimas Avižienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Daniel Dabbelt, John Hauser, and Adam Izraelevitz. 2016. The Rocket Chip Generator. EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, 4 (2016).
4. Krste Asanović , David A Patterson , and Christopher Celio . 2015. The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive , Synthesizable, Parameterized RISC-V Processor. EECS Department , University of California , Berkeley, Tech . Rep. UCB/EECS- 2015 -167. Krste Asanović, David A Patterson, and Christopher Celio. 2015. The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor. EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-167.
5. Graph Partitioning and Graph Clustering