Design and Implementation of RNB multiplier Using NP Domino logic
Author:
Affiliation:
1. G. Narayanamma Institute of Technology and Science,Department of Electronics and Communication Engineering,Hyderabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10093234/10093245/10093545.pdf?arnumber=10093545
Reference24 articles.
1. High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis
2. A testable NORA CMOS serial-parallel multiplier
3. Efficient multiplication beyond optimal normal bases
4. CMOS design of low power high speed NP domino logic;rai;IOSR Journal of VLSI and Signal Processing (IOSR-JVSP),2016
5. Various low power techniques for CMOS circuits;kalyani;International Journal of Engineering Research and Application (IJERA),2013
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