Optimal configuring of multiple scan chains

Author:

Narayanan S.,Gupta R.,Breuer M.A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Cited by 32 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Trojan playground: a reinforcement learning framework for hardware Trojan insertion and detection;The Journal of Supercomputing;2024-03-18

2. Test Point Insertion for Multi-Cycle Power-On Self-Test;ACM Transactions on Design Automation of Electronic Systems;2022-09-13

3. Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester;2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS);2021-06-28

4. Balanced Scan Chain Analysis to Improve Fault Coverage in VLSI circuits;2021 6th International Conference on Inventive Computation Technologies (ICICT);2021-01-20

5. Aggressive Exclusion of Scan Flip-Flops from Compression Architecture for Better Coverage and Reduced TDV: A Hybrid Approach;Journal of Low Power Electronics and Applications;2019-05-29

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