Test Point Insertion for Multi-Cycle Power-On Self-Test

Author:

Wang Senling1ORCID,Zhou Xihong1ORCID,Higami Yoshinobu1ORCID,Takahashi Hiroshi1ORCID,Iwata Hiroyuki2ORCID,Maeda Yoichi2ORCID,Matsushima Jun2ORCID

Affiliation:

1. Graduate School of Science and Engineering, Ehime University

2. Renesas Electronics Corporation

Abstract

Under the functional safety standard ISO26262, automotive systems require testing in the field, such as the power-on self-test (POST). Unlike the production test, the POST requires reducing the test application time to meet the indispensable test quality (e.g., >90% of latent fault metric) of ISO26262. This article proposes a test point insertion technique for multi-cycle power-on self-test to reduce the test application time under the indispensable test quality. The main difference to the existing test point insertion techniques is to solve the fault masking problem and the fault detection degradation problem under the multi-cycle test. We also present the method to identify a user-specified amount of test points that could achieve the most scan-in pattern reduction for attaining a target test coverage. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average to achieve 90% stuck-at fault coverage confirming the effectiveness of the proposed method.

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Reference38 articles.

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4. Optimal configuring of multiple scan chains

5. Embedded Deterministic Test

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