Author:
Tsai Tsai-Ling,Li Jin-Fu,Hsu Chun-Lung,Sun Chi-Tien
Cited by
17 articles.
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1. Comparative Evaluation of 6T, 8T and 10T Ternary SRAM Cells Schemes for Future VLSI and Power Electronics;2024 Second International Conference on Smart Technologies for Power and Renewable Energy (SPECon);2024-04-02
2. A Dynamic Testing Scheme for Resistive-Based Computation-In-Memory Architectures;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
3. Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03
4. R-inmac: 10T SRAM based reconfigurable and efficient in-memory advance computation for edge devices;Analog Integrated Circuits and Signal Processing;2023-09
5. In-Memory Computing with 6T SRAM for Multi-operator Logic Design;Circuits, Systems, and Signal Processing;2023-08-19