Author:
Frankiewicz Maciej,Kocanda Piotr,Gal Ryszard,Kos Andrzej
Cited by
2 articles.
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1. Implementation of MIPS RISC Processor with Flexible 5-Stage Pipelining and Dynamic Thermal Control;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28
2. MIPS Based 32-Bit RISC Processor with Thermal Management Unit and Flexible Pipelining Structure;2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON);2022-12-02