Implementation of MIPS RISC Processor with Flexible 5-Stage Pipelining and Dynamic Thermal Control
Author:
Affiliation:
1. Sai Vidya Instuitue of Technology,Dept.Electronics and Communication Engineering,Bengaluru,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10624684/10624740/10624864.pdf?arnumber=10624864
Reference15 articles.
1. Design and Analysis of A 32- bit Pipelined MIPS Risc Processor;Indira,2019
2. Design of RISC microcontroller with Dynamic Thermal Management Unit for Temperature-Controlled Oscillator
3. Low power implementation of 32-bit RISC processor with pipelining;Sneha,2019
4. A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications
5. Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA;Qui,2020
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