Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 μm CMOS-Reference-Cited by-同舟云学术

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Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 μm CMOS

Published: Issue: Volume: Page:
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Container-title:Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.
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Author:

Quinn P.,Pribytko M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/8830/27953/01249433.pdf?arnumber=1249433

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Multiplying Digital to Analog Converter Insensitive to Component Mismatch;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

2. An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors;Analog Integrated Circuits and Signal Processing;2014-04-16

3. A reference-free 7-bit 500 MS/s pipeline ADC using current-mode reference shifting and quantizers with built-in thresholds;Analog Integrated Circuits and Signal Processing;2013-02-07

4. Switched-capacitor multiply-by-two amplifier with reduced capacitor mismatches sensitivity and full swing sample signal common-mode voltage;Journal of Semiconductors;2012-11

5. A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration;IEEE Journal of Solid-State Circuits;2011-11

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