An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors-Reference-Cited by-同舟云学术

An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors

Published:2014-04-16 Issue:1 Volume:80 Page:49-57
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Kim Yong-Min,Park Jun-Sang,Shin Yong-Jin,Lee Seung-Hoon

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-014-0298-9.pdf

Reference17 articles.

1. Kim, Y. J., et al. (2008). A low offset rail-to-rail 12 b 2 MS/s 0.18 µm CMOS cyclic ADC. In IEEE APCCAS (pp. 17–20).

2. Furuta, M., Nishikawa, Y., Inoue, T., & Kawahito, S. (2007). A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters. IEEE Journal of Solid-State Circuits, 42(4), 766–774.

3. Quinn, P. & Pribytko, M. (2003). Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 µm CMOS. In Proceedings of CICC (pp. 425–428).

4. Wang, Z., et al. (2010). An in-situ temperature-sensing interface based on a SAR ADC in 45 nm LP digital CMOS for the frequency-temperature compensation of crystal oscillators. In ISSCC Digest of Technical Papers (pp. 316–317).

5. Chen, Y., Tsukamoto, S. & Kuroda T. (2009). A 9 b 100 MS/s 1.46 mW SAR ADC in 65 nm CMOS. In Proceedings of ASSCC (pp. 145–148).

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