20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process-Reference-Cited by-同舟云学术

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20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process

Published:2007 Issue: Volume: Page:
ISSN:
Container-title:2007 IEEE Custom Integrated Circuits Conference
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Author:

Singh Pratap Narayan,Kumar Ashish,Debnath Chandrajit,Malik Rakesh

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4405666/4405667/04405710.pdf?arnumber=4405710

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Distributed In-Memory Computing on Binary RRAM Crossbar;ACM Journal on Emerging Technologies in Computing Systems;2017-05-13

3. Systematic design approach for a gain boosted telescopic OTA with cross‐coupled capacitor;IET Circuits, Devices & Systems;2017-04-18

4. Distributed In-Memory Computing on Binary Memristor-Crossbar for Machine Learning;Advances in Memristors, Memristive Devices and Systems;2017

5. A 10-bit 250 MSPS charge-domain pipelined ADC with replica controlled PVT insensitive BCT circuit;Journal of Semiconductors;2015-05

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