ADC based on a fully differential current mode integrator
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-019-01456-4.pdf
Reference20 articles.
1. Inanlou, R., Shahghasemi, M., & Yavari, M. (2013). A noise-shaping SAR ADC for energy limited applications in 90 nm CMOS technology. Analog Integrated Circuits Signal Process, 77(2), 257–269.
2. Dai, R., Zheng, Y., Wang, Z., Zhu, H., Kong, W., & Zou, S. (2014). A 10-bit 2.5-MS/s SAR ADC with 60.46 dB SNDR in $$0.13~\upmu \text{ m }$$ 0.13 μ m CMOS technology. Analog Integrated Circuits Signal Process, 80(2), 255–261.
3. Dasarahalli Narasimaiah, J., Tonse, L., & Bhat, M. (2018). 11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energy-efficient successive approximation register ADC in 90 nm complementary metal-oxide-semiconductor. IET Circuits, Devices & Systems, 12(3), 249–255.
4. Joshi, A., Shrimali, H., & Sharma, S. (2017). Systematic design approach for a gain boosted telescopic OTA with cross-coupled capacitor. IET Circuits, Devices & Systems, 11(3), 225–231.
5. Singh, P., Kumar, A., Debnath, C., et al. (2007). 20 mW, 125 Msps, 10 bit pipelined ADC in 65 nm standard digital CMOS process. In IEEE custom integrated circuits conference, CICC 2007, (pp. 189–192).
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