A Foreground LSB-Based Capacitor Mismatch Calibration Method in An 18-bit SAR ADC
Author:
Affiliation:
1. College of Electronic and Information Engineering, Tongji University,Shanghai,China,201800
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10182124.pdf?arnumber=10182124
Reference8 articles.
1. Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy
2. All-Digital Background Calibration of a Successive Approximation ADC Using the “Split ADC” Architecture
3. A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS
4. An 18b 12. 5MHz ADC with 93dB SNR;hurrell;IEEE Int Solid-State Circuits Conf,2010
5. A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration
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1. A 18-bit 1-MS/s fully-differential SAR ADC with digital calibration achieving 96.1 dB SNDR;Microelectronics Journal;2024-09
2. An Improved Foreground Calibration Method for Capacitor Mismatch in NS-SAR ADC;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. On the Application of Data Weighted Averaging to Noise Shaping SAR ADCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
4. A capacitive mismatch calibration method for SAR ADCs based on TDC;Electronics Letters;2024-02
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