Hierarchical Test Integration Methodology for 3-D ICs-Reference-Cited by-同舟云学术

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Hierarchical Test Integration Methodology for 3-D ICs

Published:2015-08 Issue:4 Volume:32 Page:59-70
ISSN:2168-2356
Container-title:IEEE Design & Test
language:
Short-container-title:IEEE Des. Test

Author:

Che-Wei Chou ,Jin-Fu Li ,Yun-Chao Yu ,Chih-Yen Lo ,Ding-Ming Kwai ,Yung-Fa Chou

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/6221038/7140848/07096969.pdf?arnumber=7096969

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC's;2022 IEEE International Test Conference India (ITC India);2022-07-24

2. 3-D IC: An Overview of Technologies, Design Methodology, and Test Strategies;Advances in Intelligent Systems and Computing;2020-11-24

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