Quick Design of a Superjunction Considering Charge Imbalance Due to Process Variations
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9146596/09110714.pdf?arnumber=9110714
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Charge Imbalance Tolerance of 4H-SiC Superjunction Devices Featuring Breakdown Path Variation;IEEE Electron Device Letters;2023-07
2. A novel SiC high-k superjunction power MOSFET integrated Schottky barrier diode with improved forward and reverse performance;Journal of Semiconductors;2023-05-01
3. Design of the Drift Layer of 0.6 – 1.7 kV Power Silicon Carbide MOSFETs for Enhanced Short Circuit Withstand Time;2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2023-03-07
4. Novel High-Tolerance Termination With Resistive Field Plate for 600 V Super-Junction Vertical Double-Diffused MOSFET;IEEE Electron Device Letters;2022-07
5. Optimum Aspect Ratio of Superjunction Pillars Considering Charge Imbalance;IEEE Transactions on Electron Devices;2021-04
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