Testing station using a 0.3-mm-pitch LGA interface for a 25-Gbaud x 16-channel CPO transceiver
Author:
Affiliation:
1. Furukawa Electric Co., Ltd.,Telecommunications & Energy Laboratories,Chiba,Japan,290-8555
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10034668/10034662/10034694.pdf?arnumber=10034694
Reference5 articles.
1. 56-Gb/s PAM4 × 8-Channel VCSEL-Based Optical Transceiver for Co-Packaged Optics
2. Novel Packaging Structure Using VCSEL Array and Multi-Core Fiber for Co-Packaged Optics
3. Design of CPO Daughter Board with FPGA and 25-Gbaud × 16-Channel Ultra-Compact Optical Transceivers
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Bandwidth Expansion of a Testing Station Using a 0.3-mm-Pitch LGA Interface for a $25\text{-Gbaud} \times 16- \text{Channel}$ CPO Transceiver;2023 IEEE CPMT Symposium Japan (ICSJ);2023-11-15
2. Jitter Margin Analysis of 56-Gb/s $\text{PAM}4\times 8-\text{Channel}$ VCSEL-Based Optical Transceiver for Co-Packaged Optics;2023 IEEE CPMT Symposium Japan (ICSJ);2023-11-15
3. Co-Packaged Optics向け超小型光トランシーバ技術;Journal of The Japan Institute of Electronics Packaging;2023-05-01
4. Novel Packaging Structure Using VCSEL Array and Multi-Core Fiber for Co-Packaged Optics;2022 IEEE CPMT Symposium Japan (ICSJ);2022-11-09
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