Accelerating BPTT-Based SNN Training with Sparsity-Aware and Pipelined Architecture
Author:
Affiliation:
1. CenBRAIN Neurotech Center of Excellence, School of Engineering, Westlake University,Hangzhou,Zhejiang,China
2. Hong Kong University of Science and Technology,Department of ECE,Hong Kong SAR,China
Funder
Westlake University
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558101.pdf?arnumber=10558101
Reference16 articles.
1. C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation
2. A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking
3. 22.6 ANP-I: A 28nm 1.5pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-O.1 μJ/Sample On-Chip Learning for Edge-AI Applications
4. Early Termination Based Training Acceleration for an Energy-Efficient SNN Processor Design
5. 7.6 A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback
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