A 0.77-pJ/bit 40-Gb/s/pin Single-Ended Hybrid DAC-Based Transmitter for Memory Interfaces
Author:
Affiliation:
1. Seoul National University,Dept. of Electrical and Computer Engineering,Seoul,Korea
2. Sejong University,Dept. of Semiconductor Systems Engineering,Seoul,Korea
3. SK Hynix,Dept. of DRAM Design,Icheon,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558361.pdf?arnumber=10558361
Reference12 articles.
1. A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface
2. An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling
3. A 16/32-Gb/s/pin Dual-Mode Single-Ended Transmitter with Pre-Emphasis FFE and RLM-Enhanced ZQ Calibration for Memory Interfaces
4. A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET
5. 8.3 An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7nm CMOS
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