A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology
Author:
Affiliation:
1. The University of Electro-Communications (UEC),Tokyo,Japan
2. The University of Tokyo,Tokyo,Japan
Funder
Japan Science and Technology Agency
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558343.pdf?arnumber=10558343
Reference35 articles.
1. Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling
2. ULTRARAM: Toward the Development of a III–V Semiconductor, Nonvolatile, Random Access Memory
3. Vertical p–i–n Polysilicon Diode With Antifuse for Stackable Field-Programmable ROM
4. Unified 0.75pJ/Bit TRNG and Attack Resilient 2F2/Bit PUF for Robust Hardware Security Solutions with 4-layer Stacking 3D NbOx Threshold Switching Array
5. In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology
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