1. Adaptive Time-Triggered Network-on-Chip Architecture: Enhancing Safety;2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2023-12-29
2. Design of Fault-Tolerant and Reliable Networks-on-Chip;2015 IEEE Computer Society Annual Symposium on VLSI;2015-07
3. New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections;International Journal of Electronics and Telecommunications;2015-03-01
4. A Routing-Level Solution for Fault Detection, Masking, and Tolerance in NoCs;2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing;2015-03
5. A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC;Microelectronics Journal;2013-03