An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects-Reference-Cited by-同舟云学术

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An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects

Published:2010-01 Issue: Volume: Page:
ISSN:
Container-title:2010 23rd International Conference on VLSI Design
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Author:

Saini Sandeep,Kumar A. Mahesh,Veeramachaneni Sreehari,Srinivas M.B.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5400049/5401179/05401211.pdf?arnumber=5401211

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Digital Backend Optimization Techniques for Post-Route and Sign-Off Challenges in ASIC Design;Proceedings of Second International Conference on Computational Electronics for Wireless Communications;2023

2. Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM technologies;Nanotechnology for Environmental Engineering;2022-05-11

3. Optimized Crosstalk Circuit for Long Wire Copper Interconnects using 45nm CMOS Inverter;2020 IEEE International Women in Engineering (WIE) Conference on Electrical and Computer Engineering (WIECON-ECE);2020-12-26

4. Performance analysis of carbon nanotubes forfuture highspeed VLSI on-chip interconnect applications;JOURNAL OF MECHANICS OF CONTINUA AND MATHEMATICAL SCIENCES;2019-08-28

5. Comparative Performance Analysis of Different High-Speed Buffer Drivers Using BiCMOS Technology and MVL Logic;Lecture Notes in Electrical Engineering;2019

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