Low-Latency and High-Bandwidth Pipelined Radix-64 Division and Square Root Unit
Author:
Affiliation:
1. Arm Cambridge Design Center
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9973813/9974162/09974295.pdf?arnumber=9974295
Reference14 articles.
1. 1 GHz HAL SPARC64/sup R/ Dual Floating Point Unit with RAS features
2. Performance/Power Space Exploration for Binary64 Division Units
3. Floating point division and square root algorithms and implementation in the AMD-K7/sup TM/ microprocessor
4. High-speed double-precision computation of reciprocal, division, square root, and inverse square root
5. The Floating-Point Unit of the Jaguar x86 Core
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Unified Digit Selection for Radix-4 Recurrence Division and Square Root;IEEE Transactions on Computers;2024-01
2. Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units;IEEE Transactions on Computers;2023-10
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