Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder-Reference-Cited by-同舟云学术

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Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder

Published:2022-12 Issue:6 Volume:39 Page:119-127
ISSN:2168-2356
Container-title:IEEE Design & Test
language:
Short-container-title:IEEE Des. Test

Author:

Gomes Jiovana Sousa¹^ORCID,Bitencourt Tulio Pereira²^ORCID,Bampi Sergio²^ORCID,Ramos Fabio Luis Livi¹^ORCID

Affiliation:

1. Federal University of Pampa, Bage, Brazil

2. Informatics Institute Federal University of Rio Grande do Sul, Porto Alegre, Brazil

Funder

Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior

Conselho Nacional de Desenvolvimento Cient?fico e Tecnol?gico

Funda??o de Amparo ? Pesquisa do Estado do Rio Grande do Sul

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/6221038/9929267/09807340.pdf?arnumber=9807340

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Area and Power Efficient 8K Real-Time Design for AV1 Arithmetic Decoding;2022 Picture Coding Symposium (PCS);2022-12-07

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