Area and Power Efficient 8K Real-Time Design for AV1 Arithmetic Decoding
Author:
Affiliation:
1. Federal University of Pampa,Brazil
2. Informatics Institute, Federal University of Rio Grande do Sul,Brazil
Funder
Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10017992/10017993/10017997.pdf?arnumber=10017997
Reference16 articles.
1. Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder
2. Arithmetic coding revisited
3. AOM Reference Software,2020
4. Objective-2-fast video data set,2021
5. Compression Efficiency and Computational Cost Comparison between AV1 and HEVC Encoders
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. AV1 Residual Syntax Elements Assessment and Efficient VLSI Architecture;2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2023-08-28
2. Power Reduction Opportunities on End-User Devices in Quality-Steady Video Streaming;2023 15th International Conference on Quality of Multimedia Experience (QoMEX);2023-06-20
3. Analysis of AV1 Arithmetic Decoder Design Space with a Novel Multi-Boolean Approach;2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS);2023-02-27
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