Design of an Area Efficient Quantum Dot Cellular Automata Based Full Adder Cell Having Low Latency

Author:

Joy Upal Barua1,Chakraborty Shourov1,Tasnim Sumaiya2,Hossain Md Shahadat1,Siddique Abdul Hasib3,Hasan Mehedi1

Affiliation:

1. University of Science and Technology,Department of Electrical and Electronics Engineering,Chittagong,Bangladesh

2. Deakin University,Department of Electrical and Electronics Engineering,Melbourne,Australia

3. Khalifa University,Department of Electrical and Electronics Engineering,Abu Dhabi,UAE

Publisher

IEEE

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. CMOS Implementation of a Piecewise Linear Activation Function Based Neuron Unit for Neural Network Accelerator;2024 2nd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT);2024-03-15

2. Design and implementation of carry-save adder using quantum-dot cellular automata;The Journal of Supercomputing;2023-07-19

3. Quantum-Dot Cellular Automata-Based Full Adder Design: Comprehensive Review and Performance Comparison;Advances in Materials Science and Engineering;2023-01-10

4. Performance Enhancement of Conventional Design of 4-Bit Carry Look-Ahead Adder;2023 3rd International Conference on Robotics, Electrical and Signal Processing Techniques (ICREST);2023-01-07

5. Two-Bit Magnitude Comparator Design Using Gate Diffusion Input Technique and Static CMOS Logic;2023 3rd International Conference on Robotics, Electrical and Signal Processing Techniques (ICREST);2023-01-07

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