Analysis of the behavior of a dynamic latch comparator-Reference-Cited by-同舟云学术

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Analysis of the behavior of a dynamic latch comparator

Published:1998-03 Issue:3 Volume:45 Page:294-298
ISSN:1057-7122
Container-title:IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Cusinato P.,Bruccoleri M.,Caviglia D.D.,Valle M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx4/81/14515/00662703.pdf?arnumber=662703

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration;IEEE Journal of Solid-State Circuits;2019-01

3. A Frequency-Domain Analysis of Latch Comparator Offset due to Load Capacitor Mismatch;IEEE Transactions on Circuits and Systems II: Express Briefs;2015-06

4. A comparison between high-pass and low-pass $$\Updelta\Upsigma$$ modulators;Analog Integrated Circuits and Signal Processing;2012-07-28

5. A Comparative Study of Loop Filter Alternatives in Second-Order High-Pass $\Delta\Sigma$ Modulators;IEEE Transactions on Circuits and Systems I: Regular Papers;2011-11

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