Research on Noise Simulation of Dynamic Comparator-Reference-Cited by-同舟云学术

Research on Noise Simulation of Dynamic Comparator

Published:2021-10-22 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2021 5th International Conference on Electronic Information Technology and Computer Engineering
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Author:

Liu Yinghao¹,Wang Xiaoman¹,Yang Xiaokun¹,Li Jinwang¹,Liu Chang¹,Xu Liguo¹

Affiliation:

1. Master Control Chip R&D Department, Beijing Smartchip Microelectronics Technology Company Limited, Beijing, People's Republic of China

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3501409.3501425

Reference10 articles.

1. Analysis of the behavior of a dynamic latch comparator

2. Jeon H J , Kim Y B . A CMOS low-power low-offset and high-speed fully dynamic latched comparator[C]// Soc Conference . IEEE , 2010 . Jeon H J, Kim Y B. A CMOS low-power low-offset and high-speed fully dynamic latched comparator[C]// Soc Conference. IEEE, 2010.

3. Yinghao L , Dejian L , Baodong Y , Noise simulation method and system of dynamic comparator :, CN110348157A[P]. 2019 . Yinghao L, Dejian L, Baodong Y, et al. Noise simulation method and system of dynamic comparator:, CN110348157A[P]. 2019.

4. A 10-bit 2 Ms/S SAR ADC with Vcm-Based Switching Scheme[J];Yinghao L;Microelectronics & Computer,2017

5. Schinkel D , Mensink E , Klumperink E , A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time[C]// Solid-State Circuits Conference, 2007 . ISSCC 2007 . Digest of Technical Papers. IEEE International. IEEE , 2007 :314--605. Schinkel D, Mensink E, Klumperink E, et al. A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time[C]// Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International. IEEE, 2007:314--605.